FIG. 7 is a diagram, illustrating a cross-sectional structure of a semiconductor device according to a conventional technology. Such semiconductor device is reported by, for example, Imanaga et al. in Patent Document 1. In FIG. 7, reference numeral 100 indicates a sapphire substrate, which is a substrate of (0001) face, namely C face, reference numeral 101 indicates a buffer layer, reference numeral 102 indicates an electron-supplying layer composed of N-type aluminum gallium nitride (AlzGa1-zN) (hereinafter, referred to as AlGaN electron-supplying layer), reference numeral 103 indicates a channel layer composed of gallium nitride (GaN) (hereinafter, referred to as GaN channel layer), and reference numeral 104 indicates an insulating layer composed of undoped aluminum nitride (AlN) (hereinafter referred to as AlN insulating layer). A source electrode 10S and a drain electrode 10D is formed on the AlN insulating layer 104 to create ohmic contacts. A gate electrode 10G is formed in a location disposed between the source electrode 10S and the drain electrode 10D on the AlN insulating layer 104 to create a Schottky contact. Such semiconductor device is referred to as a semiconductor device having a double heterostructure.
FIG. 8 is an energy band diagram under a gate in a semiconductor device shown in FIG. 7. In the double heterostructure, two-dimensional electron gas 107 is generated in vicinity of an interface of the GaN channel layer 103 with the AlGaN electron-supplying layer 102 and in vicinity of an interface of the GaN channel layer 103 with the AlN insulating layer 104. The band gap of AlN constituting the AlN insulating layer 104 is larger in this structure, which leads to characteristics of enhanced Schottky barrier and improved forward gate breakdown voltage of the semiconductor device.
Besides, Imanaga et al. also reports in Patent Document 2 a semiconductor device of the double heterostructure, in which the AlN insulating layer of Patent Document 1 is replaced with a multiple-layered structure of an AlN layer and a silicon dioxide (SiO2) layer.
Further, Patent Document 3 and Non-Patent Document 1 disclose semiconductor devices having structures, in which the respective layers of AlGaN/GaN/AlGaN insulating layer stacked in this sequence on a substrate.
Besides, a semiconductor device having a silicon nitride (SiN) insulating film provided on a double heterostructure of GaN/N-type AlGaN/GaN is reported in Patent Document 4. Since interface charges generated in two heterointerfaces cancel each other out in this structure, no two-dimensional electron is generated in a thermal equilibrium state of Vg=0 V to allow an enhancement operation.
Further, C. T. Lee et al. discloses in Non-Patent Document 2 a semiconductor device provided with an insulating film composed of a multiple-layered member of gallium oxide (Ga2O3) and SiO2 formed on an N-type GaN channel layer, and also reports a semiconductor device having a metal-insulator-semiconductor (referred to as “MIS”) structure.
Patent Document 1
    Japanese Patent Laid-Open No. 2000-294,768Patent Document 2    Japanese Patent Laid-Open No. 2000-252,458Patent Document 3    Japanese Patent Laid-Open No. H11-261,052 (1999)Patent Document 4    Japanese Patent Laid-Open No. 2004-335,960Non-Patent Document 1    IEEE Electron Device Letters, Vol. 18, pp. 293 to 295, 1997Non-Patent Document 2    IEEE Electron Device Letters, Vol. 24, pp. 54 to 56, 2003